EDIF - Electronic Design Interchange Format - is a vendor neutral format in which to store Electronic netlists and schematics. It was one of the first attempts to establish a neutral data exchange format for the electronic design automation (EDA) industry. Electronic Data Interchange Format file. An industry standard file format for specifying a design netlist. WMDB – Windows Media Database file – The CurrentDatabase360.wmdb file can contain file name, file properties, music, video, photo and playlist information. Big Data (Distributed) edit Avro - Data format appropriate for ingestion of record based attributes.
EDIF Input File (.edf)
An EDIF version 2 0 0 netlist file (with the extension (.edf), generated by any standard EDIF netlist writer. The Quartus® II software also supports EDIF Input files with the extension (.edif)
When you compile an EDIF Input File, the Compiler uses one or more Library Mapping Files (.lmf) to map cells in an EDIF Input File to corresponding Quartus II logic functions, including Library of Parameterized Modules (LPM) functions, as well as to user-defined functions.
All logic functions in an EDIF Input File must be mapped to the Quartus II software logic functions in a Library Mapping File (.lmf). If you wish to use a function that is not mapped in a Altera-provided LMF, you must create a customized LMF. You can map EDIF cells to Altera-provided functions or to any design file created with the Quartus II software.
The Compiler processes EDIF Input Files automatically, generating a Compiler Netlist Extractor (.cnf) file for every cell in an EDIF Input File. You can also specify EDIF Input settings to help the Compiler interpret EDIF Input Files by specifying optional LMFs and non-default VCC and GND signal names.
A single EDIF Input File can be used to define all logic in a project, or can be incorporated at any hierarchy level in a hierarchical project.
The Quartus II software automatically creates a Block Symbol File (.bsf) that represents an EDIF Input File when you open the file in the Text Editor and create the default symbol for the current file. This symbol and the logic it represents can be incorporated into a Block Design File (.bdf).
You can also use EDIF Input File logic in an AHDL Text Design File (.tdf) by including a Function Prototype and inserting an instance of the function into the TDF.
You can import some resource assignments into the Quartus II software with the following EDIF property constructs:
| Construct: | Type of Assignment: |
| chip_pin_lc | Chip, pin, logic cell |
| clique | clique |
| logic_option | Logic option |
As an alternative, you can use the Assignment Organizer in the Quartus II software to make all types of assignments--including location and device assignments--for the logic in the EDIF Input File.
To properly convert an EDIF Input File, EDIF constructs must have the following values:
| Construct: | Value: |
| edifLevel | 0 |
| keywordLevel | 0 |
| viewType | NETLIST |
| cellType | GENERIC |
The file name may be truncated to 8 characters. If you truncate the file name, you must then either rename the file with its previous longer file name from within the Quartus II software, or edit the file to change any instances of the file name to the new, truncated name. To rename the file from within the Quartus II software, open the file with the truncated name in the Text Editor and save it to its previous longer file name. However, if your file transfer software inserts characters into the truncated name that are not legal Quartus II software name characters, you may need to first rename the file from the DOS command line before you can open it in the Text Editor.
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Edif File Format
Yosys is a framework for Verilog RTL synthesis. It currently hasextensive Verilog-2005 support and provides a basic set ofsynthesis algorithms for various application domains. Selected featuresand typical applications:
- Process almost any synthesizable Verilog-2005 design
- Converting Verilog to BLIF / EDIF/ BTOR / SMT-LIB / simple RTL Verilog / etc.
- Built-in formal methods for checking properties and equivalence
- Mapping to ASIC standard cell libraries (in Liberty File Format)
- Mapping to Xilinx 7-Series and Lattice iCE40 FPGAs
- Foundation and/or front-end for custom flows
Edif Netlist File Format Download
Yosys can be adapted to perform any synthesis job by combiningthe existing passes (algorithms) using synthesis scripts andadding additional passes as needed by extending the Yosys C++code base.
Yosys is free software licensed under the ISC license (a GPLcompatible license that is similar in terms to the MIT license or the2-clause BSD license).
Example Usage
Yosys is controlled using synthesis scripts. For example, the followingYosys synthesis script reads a design (with the top module mytop) fromthe verilog file mydesign.v, synthesizes it to a gate-level netlistusing the cell library in the Liberty file mycells.lib and writes thesynthesized results as Verilog netlist to synth.v:
Netlist File Format
The synth command provides a good default script that can be usedas basis for simple synthesis scripts:
See help synth for details on the synth command.